Welcome![Sign In][Sign Up]
Location:
Search - qpsk xilinx

Search list

[Graph programxapp208

Description: xilinx 基于查找表方法实现的IDCT的verilog源码-Xilinx LUT-based method to achieve the IDCT of the Verilog source code
Platform: | Size: 8192 | Author: lee | Hits:

[Communication-MobileXilinx-FPGA-Matlab-Simulate

Description: Xilinx的FPGA 中的matlab simulink建模,内有几种调制方式,比如QPSK等-Xilinx
Platform: | Size: 228352 | Author: 中山太乙 | Hits:

[DocumentsQPSK

Description: 提出了一个采用(2,1,7)卷积码+QPSK的中频调制解调方案,并在Xilinx公司的100万 门FPGA芯片上实现了该系统。该系统在信噪比SNR为6dB左右时可实现速率超过1Mbit/s、误码率 小于10-5的数据传输。 -Proposed a use of (2,1,7) convolutional code+ QPSK modulation and demodulation of the IF program, and in Xilinx' s FPGA chip one million on implementation of the system. The system SNR to 6dB signal to noise ratio at about the rate may achieve more than 1Mbit/s, less than 10-5 bit error rate of data transmission.
Platform: | Size: 62464 | Author: 张同星 | Hits:

[matlabASK-OOK-FSK-BPSK

Description: MATLAB实现ASK, OOK, FSK, BPSK, QPSK, 8PSK调制源代码-Free Source Code for ASK, OOK, FSK, BPSK, QPSK, 8PSK Digital Modulation in FPGAs Xilinx using system generator (ASK, BPSK, FSK, OOK, QPSK)
Platform: | Size: 57344 | Author: chenkui | Hits:

[Linux-UnixXilinx-FPGA-Matlab-Simulate

Description: 这是Matlab实现的非常简单的数字信号调制仿真,用于Xilinx FPGA(ASK, BPSK, FSK, OOK, QPSK)-Matlab is very simple simulation of digital signal modulation for Xilinx FPGAs (ASK, BPSK, FSK, OOK, QPSK)
Platform: | Size: 229376 | Author: 罗生 | Hits:

[VHDL-FPGA-Verilogqpsk_demod_use_FPGA

Description: 根据软件无线电的思想,提出了一种新颖的数字信号处理算法,对QPSK信号的相位进行数字化处理,从而实现对QPSK信号的解调.该算法允许收发两端载波存在频差,用数字锁相实现收发端载波的同步,在频偏较大的情况下,估算频偏的大小,自适应设置环路的带宽,实现较短的捕获时间和较好的信噪性能。整个设计基于XILINX公司的ISE开发平台,并用Virtex-II系列FPGA实现。用FPGA实现调制解调器具有体积小、功耗低、集成度高、可软件升级、扰干扰能力强的特点,符合未来通信技术发展的方向。-According to the idea of software radio, a novel digital signal processing algorithm, the phase of QPSK digital signal processing, enabling the demodulation of QPSK signals. This algorithm allows the sending and receiving ends of the carrier frequency difference exists, using digital phase-locked to achieve synchronization of sending and receiving end of the carrier, in the case of large frequency offset, frequency offset estimation of the size, adaptive set the loop bandwidth to achieve shorter acquisition time and better noise performance. The whole design is based on the company XILINX ISE development platform, and Virtex-II series with the FPGA. FPGA realization of a modem with a small size, low power consumption, high integration, software upgrades available, the characteristics of strong interference interference, in line with the future direction of ICT development.
Platform: | Size: 64512 | Author: 马文 | Hits:

CodeBus www.codebus.net